Coding Hardware and Hardware Description Languages
In our daily life, we use programming languages to structure a program that’s going to be executed by a hardware. Did you know it’s also possible to structure a hardware (end-to-end) by using hardware description languages?
To simply put, there’re some hdls on the world but the most popular ones are Verilog and VHDL.
Verilog and VHDL has different kind of syntax. Verilog is alike C programming language and for simplicity and popularity it would be good choice to the one who is familiar with c like programming languages.
In this article i’ll show the differences of two type of languages and code a hardware by using one of the most popular hdls which is Verilog.
Here is a simple C program that allows you to decribe a software that prints “hello world” to your terminal screen.
The program says to the operating environment to include “stdio.h” and “stdlib.h” files and call the main method with additional parameters and after that print a message to the screen and exit successfully.
Here is a simple Verilog Hardware Description language that describe a hardware and says that the hardware will have 2 inputs and 1 output and the output equals to the logical “or” operation of the inputs.
when you execute the verilog program in a verilog interpreter you’ll get something like this
And when you change the inputs your circuit will behave according to your description.
Verilog has two types of coding style behavioral and structural.
Behavioral model is just like our programming languages, we simply say “what” the circuit should do as we did in the example above. the catch is how it performs the operation depends on the interpreter.
ex: such as on the hardware level there’re more than 3 types of binary adding methods (chain based adder, look ahead adder etc.) all of them has its own pros and cons. but if you define this as a+b what kind of adder is used is unclear.
Structural model is the quite opposite of the behavioral model. we describe “how” it should do the operation. in this model we define wires and connect them specifically as if we really connect a hardware in real life.
Describing A Memory
In this example we’ll describe an actual memory. This will be a little more advanced verilog example. you don’t need to understand the code just see what we can do by using holds.
- To do this i’ll use vscode and DigitalJS(verilog interpreter extension)
module data_memory #(parameter wordLen = 8) // 8bits
(input clk,input [wordLen-1:0] mem_access_addr,input [wordLen-1:0] mem_write_data,input mem_write_en,output [wordLen-1:0] mem_read_data);reg [wordLen-1:0] ram [(2**wordLen) -1 : 0];integer i;initial beginfor(i=0;i<=(2**wordLen) -1 ;i++) // 256 word memory. 256Byte ram[i] <= 0;
ram[4] = 240; // initial data to read from cell.endalways @(posedge clk) beginif (mem_write_en)ram[mem_access_addr] <= mem_write_data;endassign mem_read_data = ram[mem_access_addr];endmodule
I added additional line for 4th memory cell and set it to 240. so when we give the 4th memory address, we expect to get the data as output.
Here’s the hardware schematics of the hdl.
as you can see that in the cells each of the cells are 0 except the 4th memory address.
When i set the mem_access_addr on the left bottom side of the controller i read the value of 240(0xf0) from the cell as a result.
To set a data to out memory first we’ll need to supply the memory address and the value that we’ll put and we must set the mem_write_en input to 1.
On the rising edge of the clock the value will be set to the corresponding memory address as it’s showed below.
It’s also very possible to create multiple modules and use each one of them in a huge module, thus you can create any kind of digital hardware. In the next chapter I’ll show you more modules and at the end put each back to back and design an actual processor by using Verilog.
Thanks for the reading
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